Retro Challenge 2024 #1

Introduction

During previous RetroChallenges I made an 8-bit HD6309 system and implemented a speech synthesizer on a Digilent DE0 FPGA board. Both were fun projects.

I’ve always wanted to do more with the Motorola 68000, primarily because it is more powerful than an 8-bit system, has a nice orthogonal instruction set and a large flat memory model, unlike the Intel 8086. This generally makes it easier to write software.

Unfortunately I don’t have a 68000 processor or a vintage system based on it, so I thought I’d take the FPGA route again and (try to) implement a bare-bones 68000 system with that.

The Digilent DE0 FPGA board I used previously is quite expensive and the development software is bloated; not really easy going on the hobbyist one might say. In the past few years things have changed. The open source community has reverse-engineerd the low-cost Lattice ICE40 series and some Gowin FPGAs. A logic synthesis package is available in the form of Yosys, place and route tools for the aforementioned FPGAs are provided by nextpnr in combination with Icestorm, Trellis and Apicula.

Given the above, I chose to use the TEC0117 FPGA board from Trenz Electronic. At 34 Euros ex. shipping it is affordable but still quite capable. The Gowin GW1NR FPGA is (hopefully) large enough to hold a 68000 design. It also features 8 megabytes of embedded synchronous SRAM which I’ll use as system RAM. And it has a build-in serial to USB chip to provide terminal access. The onboard 8 megabyte SPI flash chip can provide disk storage. Last but not least: it’s supported by the open source tools!

Let’s see how far I get!

Toolchain test

Aaaaand I’ve just heard from the Apicula developers that the embedded SDRAM is not (yet) supported by the open source tools. That is a bit of a setback…

See part two of this series.

As a backup for the open source tools, there are still the official Gowin tools. But I’ll try the open source tools first.

Offical Gowin tools

To run the official Gowin tools on Ubuntu 24.04 you have to preload a library, because making software is hard..

#!/usr/bin/sh
if [ -L /usr/lib/x86_64-linux-gnu/libfreetype.so.6 ];then
    export 'LD_PRELOAD=/usr/lib/x86_64-linux-gnu/libfreetype.so.6' 
fi
exec ./gw_ide

Embedded SDRAM notes

The 8 megabyte embedded SDRAM is poorly documented. The datasheet states:

The SDRAM integrated in the GW1NR series of FPGA Products is a
high-speed CMOS synchronous DRAM with a capacity of 64M bits. The
SDRAM consists of four banks with each bank containing 1M x16 bits.
Each bank is organized as 4096 rows x 256 columns x 16 bits. Burst
accesses are supported. Accesses start at a selected location and
continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Activate command,
which is then followed by a Read or Write command. The SDRAM provides
read or write burst lengths of 1, 2, 4, 8, or full page, with a burst termination
option. An auto pre-charge function may be enabled to provide a self-timed
row pre-charge that is initiated at the end of the burst sequence. Both the
auto-refresh and self-refresh functions are easy to use. Besides, by using a
programmable mode register, the system can choose the most suitable
modes to maximize its performance.

The datasheet also specifies it has a clock frequency of 200MHz, has a CAS latency of 2 or 3 cycles and bust lengths of 1,2,4,8 words or a full page. So perhaps this is enough information to identify which SDRAM chip they are using.

Gowin probably want to push their SDRAM controller IP. Unfortunately, the open source tools don’t have support for this – I have to write my own controller. Their IP documentation shows the command table for the SDRAM:

The initialisation sequence, read/write flow and refresh procedure are documented here.