Retro Challenge 2024 #4

Introduction

The last update was a while ago. In the mean time I’ve implemented the receive UART and tried to get the embedded SDRAM operational.

RX UART

The receive UART is more complex than the transmit UART, mostly because the receive UART needs to synchronise to the incoming bit symbols. Commercial UARTs run the receive logic at a multiple of the baud rate so the incoming signal is sampled multiple times per bit. This allows the UART to detect the start bit edge to within a fraction of the symbol time. I do the same in my VHDL implementation and run the receive logic at 4x the baud rate.

When the start bit edge is detected, the data bits are detected at the baud rate. To make sure the bits aren’t sampled on their edges, an offset of half baud time is used. This works well.

SDRAM

During the last two weeks I’ve been trying to get the SDRAM to work. Except for the memory layout paramaters (1Mbit x 4 banks x 16 bits) Gowin haven’t released any information about the timing of the SDRAM. Synchronous DRAM is a lot different from regular DRAM in that it uses a clock to read and write data. Internal pipelining logic is used to allow bursts of data to be streamed out at the full clock rate once a read request gets going. The downside is that it takes a few clock cycles to setup a read or write. In effect, a SDRAM data transfer is only efficient when used in burst mode.

The GW68000 system does not have a cache controller to keep things simple. This also means it cannot take full advantage of the SDRAM burst mode – the 68000 just reads one 16-bit word per transfer.

An additional challenge of SDRAM is that is needs a special startup sequence. The banks need to be “precharged” and the mode register needs to be configured for the desired operating characteristics. These include read and write burst length (which is 1 word in our system) and the CAS latency, which determines the number of clock cycles between an actual read request and the data appearing at the RAM output. Of course, none of this has been documented by Gowin. Luckily, this type of SDRAM is somewhat of an industry standard.

The SDRAM has names familiar to those who know about regular DRAM: RAS, CAS and WE, for example. Unfortunately, that is where the similarity ends. The three signals are used to specify commands to the SDRAM internal state machine, making interfacing to the SDRAM complicated.

The icing on the cake is that the SDRAM does not provide a status mechanism – you’re basically talking to it blindly and you have to hope for the best.

I’ve implemented about three SDRAM controllers based on the industry standard and I never got it to work. My next strategy is to try and use the Gowin SDRAM IP block, see if that works and – if so – capture the SDRAM controller signals into a file for further analysis. I intend to use the TX UART block to send the captured signals to the PC.

Theo is not impressed…

Conclusion

The GW68000 cpu works, as do the RX and TX UARTS. Hopefully I will be able to get the SDRAM working. Without a large RAM, a 68000 is not very useful.